SRAM cells (or SRAM cell structures) in general are random access memory cells that retain data bits in their memory as long as power is being supplied. SRAM is used in personal computers, workstations, routers, peripheral equipment and the like.
SRAM cells are composed of a pair of cross coupled inverters connected together to form dual (first and second) storage node outputs with opposing logic states. Therefore SRAM cells have two stable logic states. The first logic state includes a logic one (1) and a logic zero (0) at the first and second storage node outputs, respectively. The second state includes a logic 0 and a logic 1 at the same first and second storage node outputs, respectively.
The storage nodes will be connected to a pair of pass gate transistors, which are typically n-type transistors. Typically each inverter includes a p-type pull up transistor and an n-type pull down transistor. One of the pass gate transistors is connected to a bit line and the other to a bit line bar (herein collectively “the bit lines”). A word line enables the pass gate transistors to control data flow between the inverters and the bit lines during read and write operations.
Generally in a semiconductor SRAM cell, the four n-type transistors (i.e., the two pass gate and two pull down transistors) are Fin Field Effect Transistors (FinFETs) imbedded in n-type fins that extend horizontally across a substrate of a semiconductor structure. Additionally, the two p-type transistors (the two pull up transistors) of the SRAM cell are FinFETs imbedded in p-type fins that extend horizontally across the same substrate. These types of prior art SRAM cells may be referred to herein as horizontal FinFET SRAM cells, since the source/drain regions and channels of the FinFETs are all disposed horizontally relative to a substrate plane that is defined by a top surface of the substrate.
SRAM cells are constantly being down-sized to meet increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits in semiconductor structures. As such, the FinFETs of the SRAM cells need to be ever more densely packaged within the substrate plane.
However, such down-sizing provides technical challenges that become increasingly problematic, especially for horizontal SRAM cells. For example, leakage currents of FinFETs may increase as the channels within the FinFETs become smaller in length. Moreover, it becomes ever more difficult to increase the overall area (or footprint) along the substrate plane of a semiconductor structure to accommodate larger numbers of horizontal SRAM cells as complexity of the semiconductor structure increases.
Some prior art SRAM cells may alleviate some of these technical challenges by using vertical FinFETs. These prior art vertical FinFETs have fins for channels that extend vertically upwards from a bottom source/drain (S/D) region embedded in the substrate to an upper S/D region disposed above the substrate.
However, landing metal contacts on the bottom S/D regions of vertical FinFETs becomes increasingly difficult as the vertical SRAM cells are downsized. This is because the metal contacts must be placed between the upper structures, such as the gate structure, of the vertical FinFETs without making undesirable electrical contact to those upper structures. Additionally, the metal contacts of prior art vertical FinFETs generally land on the upper surface of the bottom source drain regions, which provide an ever decreasing surface area as the SRAM cells are downsized.
Moreover, the metal contacts of prior art vertical FinFETs can get unacceptably close to the vertical channels when connecting to the bottom S/D regions. If the metal contacts touch the vertical channels, the metal contacts can contaminate the channel and adversely affect performance.
Additionally, vertical SRAM cells require a cross-coupled contact between certain bottom S/D regions of one inverter and certain gate regions of the other inverter of the SRAM cells. Such cross-coupled contacts are subject to similar types of technical problems as that of the placing of the metal contacts within a vertical SRAM cell. That is, the cross-coupled contacts must be made without undesirably shorting to other structures within the SRAM cells. Also the top surface of the bottom S/D regions provide an ever decreasing target for the cross-coupled contacts to land on as the SRAM cells are downsized. Additionally, the cross-coupled contacts must not touch and contaminate the channels.
Accordingly, there is a need for a vertical SRAM cell, and method of making the same, that more reliably enables proper electrical continuity of metal contacts to the bottom S/D regions than that of prior art vertical SRAM cells. Additionally, there is a need to prevent the metal contacts and cross-couple contacts from touching and contaminating the channels.